Analog-to-digital converters (ADC's) play a fundamental role in the execution of sample detection techniques used in disk drive read channels. FIG. 1 is a block diagram showing an ADC 32 as described in commonly-assigned and copending application Ser. No. 08/288,448, filed Aug. 10, 1994, by Toan Tran ("the '448 application"). The '448 application is hereby incorporated by reference to provide additional background information regarding the present invention.
As shown in FIG. 1, the ADC 32 includes a resistive ladder network 38 that includes matching resistors connected in series to a positive voltage supply 40. The series-connected resistors, which have a mid-point voltage level V.sub.mid, are connected to a negative voltage supply via a current source 42.
As further shown in FIG. 1, ADC 32 includes a differential-to-single ended converter 44 that converts a differential analog signal Vin(diff) to a corresponding single-ended analog signal 46. Significantly, the output of the differential-to-single ended converter 44 is controlled by the mid-point voltage level V.sub.mid of the resistive ladder network 38 such that the voltage level V.sub.S of the single-ended analog read signal 46 has a DC level nominally equal to the mid-point of the resistive ladder network 38. (Those skilled in the art will appreciate that the voltage range of the analog-to-digital convertor 32 is controlled by the current pulled through the resistive ladder network 38.)
ADC 32 further includes a comparator latch bank 48 that includes a number of comparators. Each comparator in the comparator latch bank 48 receives both the single ended output signal 46 of the differential-to-single ended convertor 44 and a signal provided from an interconnection between two adjacent resistors in the resistive ladder network 38. The comparator latch bank 48 responds to the rising edges of an externally-provided clock signal CLK CLKB to provide a plurality of comparator latch bank output signals 50.
Since each of the comparators in the comparator latch bank 48 is comparing the signal output 46 of the single-ended converter 44 against reference voltage points on the resistive ladder 38 that increase and decrease from the mid-point level V.sub.mid, the output 50 of the comparator latch bank 48 comprises a sequence of 0's, representing the comparators in the latch bank 48 for which the level of the reference voltage is greater than the level of the output 46, and a sequence of 1's, representing the comparators in the latch bank 48 for which the level of the reference voltage is less than the level of the output 46.
The AND/latch bank 52 responds to pairs of adjacent bits of the so-called "thermometer code" output 50 of the comparator latch bank 48 on the falling edges of the clock signal CLK CLKB by providing a 64-bit output 54 that is unique to the signal level of the single-ended converter output 46. This 64-bit code 54 serves as the input to the decoder/output latch 56, which functions essentially as a look-up table to provide the 6-bit digital output.
The range of the ADC 32 is programmable via a 5-bit digital input to the current source 42. This allows the range of the ADC 32 to vary from 1 to 2 times V.sub.pp of the input signal. This programmability allows selection of the optimum range for reading data from each sector on the disk drive storage element 12.
The differential to single-ended converter 44 may be of the type described in commonly assigned and U.S. Pat. No. 5,432,476, also by Toan Tran the '476 patent. The '949 application is hereby incorporated by reference to provide additional background information regarding the present invention.
FIG. 2 is a block diagram illustrating a differential to single-ended converter 20 of the type described in the '476 petent. A differential input signal (V.sub.IN+, V.sub.IN-) is provided to an input buffer 22. The input buffer 22 provides the differential input V.sub.IN+, V.sub.IN- to respective V-to-I converters 24, 26. A first of the V-to-I converters 24 provides its output to a mirror unit 28. A DC level setter 30 establishes a DC voltage level which it provides to resistor means 29. The outputs of the mirror unit 28, the resistor means 29, and the second V-to-I converter 26 are combined to provide a single-ended output signal V.sub.OUT at a terminal 31. A unity voltage gain stage 27 receives the single-ended output signal V.sub.OUT from the terminal 31 and provides a single-ended drive signal V.sub.S which can drive a load.
A problem with many ADC's, including those which include a differential-to-single ended converter of the type shown in FIG. 2, is that there is typically a voltage offset (VOS) in the single-ended output signal they generate. For example, referring to differential-to-single ended converter in FIG. 2, VOS may be caused by mismatch of transistors within the input buffer 22, and this VOS evidences itself as a difference between the DC level of V.sub.S and V.sub.mid in the single-ended output signal of the differential-to-single ended converter. VOS may be caused, for example, by process variations in the fabrication of the ADC components. Similarly, operating temperature variations will cause VOS. VOS in the single-ended drive signal V.sub.S results in an error in the digital output of the ADC.
Therefore, what is desired is an ADC which can both detect and correct for VOS.